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19-0172; Rev 6; 2/97
+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs
_______________General Description
The MAX531/MAX538/MAX539 are low-power, voltageoutput, 12-bit digital-to-analog converters (DACs) specified for single +5V power-supply operation. The MAX531 can also be operated with 5V supplies. The MAX538/MAX539 draw only 140A, and the MAX531 (with internal reference) draws only 260A. The MAX538/MAX539 come in 8-pin DIP and SO packages, while the MAX531 comes in 14-pin DIP and SO packages. All parts have been trimmed for offset voltage, gain, and linearity, so no further adjustment is necessary. The MAX538's buffer is fixed at a gain of +1 and the MAX539's buffer at a gain of +2. The MAX531's internal op amp may be configured for a gain of +1 or +2, as well as for unipolar or bipolar output voltages. The MAX531 can also be used as a four-quadrant multiplier without external resistors or op amps. For parallel data inputs, see the MAX530 data sheet.
___________________________Features
o Operate from Single +5V Supply o Buffered Voltage Output o Internal 2.048V Reference (MAX531) o 140A Supply Current (MAX538/MAX539) o INL = 1/2LSB (max) o Guaranteed Monotonic over Temperature o Flexible Output Ranges: 0V to VDD (MAX531/MAX539) VSS to VDD (MAX531) 0V to 2.6V (MAX531/MAX538) o 8-Pin SO/DIP (MAX538/MAX539) o Power-On Reset o Serial Data Output for Daisy-Chaining
MAX531/MAX538/MAX539
_______________________Applications
Battery-Powered Test Instruments Digital Offset and Gain Adjustment Battery-Operated/Remote Industrial Controls Machine and Motion Control Devices Cellular Telephones
______________Ordering Information
PART MAX531ACPD MAX531BCPD MAX531ACSD MAX531BCSD MAX531BC/D TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 14 Plastic DIP 14 Plastic DIP 14 SO 14 SO Dice* ERROR (LSB) 1/2 1 1/2 1 1
________________Functional Diagram
(MAX531 ONLY) REFIN REFOUT (MAX531 ONLY) BIPOFF
Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C only.
_________________Pin Configurations
RFB (MAX531 ONLY) VOUT
2.048V REFERENCE (MAX531 ONLY)
MAX531 MAX538 MAX539
DAC
TOP VIEW
AGND POWER-UP RESET
VDD DAC REGISTER (12 BITS) CONTROL LOGIC SHIFT REGISTER (12 BITS) (MSB) (LSB) 4 BITS DGND (MAX531 ONLY) VSS (MAX531 ONLY) DOUT
DIN SCLK
1 2
8 7
VDD VOUT REFIN AGND
CLR (MAX531 ONLY) CS SCLK DIN
CS 3 DOUT 4
MAX538 MAX539
6 5
DIP/SO
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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+5V, Low-Power, Voltage-Output Serial 12-Bit DACs MAX531/MAX538/MAX539
ABSOLUTE MAXIMUM RATINGS
VDD to DGND and VDD to AGND ................................-0.3V, +6V VSS to DGND and VSS to AGND .................................-6V, +0.3V VDD to VSS .................................................................-0.3V, +12V AGND to DGND........................................................-0.3V, +0.3V Digital Input Voltage to DGND ......................-0.3V, (VDD + 0.3V) REFIN ..................................................(VSS - 0.3V), (VDD + 0.3V) REFOUT to AGND .........................................-0.3V, (VDD + 0.3V) RFB .....................................................(VSS - 0.3V), (VDD + 0.3V) BIPOFF ................................................(VSS - 0.3V), (VDD + 0.3V) VOUT (Note 1) ................................................................VSS, VDD Continuous Current, Any Pin................................-20mA, +20mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.09mW/C above +70C)....727mW 8-Pin SO (derate 5.88mW/C above +70C) ................471mW 14-Pin Plastic DIP (derate 10.00mW/C above +70C)...800mW 14-Pin SO (derate 8.33mW/C above +70C) ..............667mW Operating Temperature Ranges MAX53_ _C_ _ .....................................................0C to +70C MAX53_ _E_ _ ..................................................-40C to +85C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10sec) .............................+300C
Note 1: The output may be shorted to VDD, VSS, or AGND if the package power dissipation limit is not exceeded.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(VDD = +5V 10%, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), CREFOUT = 33F (MAX531), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER STATIC PERFORMANCE Resolution Relative Accuracy (Note 2) Differential Nonlinearity Unipolar Offset Error Unipolar Offset Tempco Gain Error (Note 2) Gain-Error Tempco Power-Supply Rejection Ratio (Note 3) VOLTAGE OUTPUT (VOUT) Output Voltage Range Output Load Regulation Short-Circuit Current REFERENCE INPUT (REFIN) Voltage Range Input Resistance Input Capacitance AC Feedthrough Code dependent, minimum at code 555 hex Code dependent (Note 4) REFIN = 1kHz, 2Vp-p 0 40 10 -80 50 VDD - 2 V k pF dB ISC MAX531 (G = +1), MAX538 MAX531 (G = +2), MAX539 VOUT = 2V, RL = 2k 12 0 0 VDD - 2 VDD - 0.4 1 V LSB mA PSRR 4.5V VDD 5.5V N INL DNL VOS TCVOS GE MAX53_ _C/E 1 0.4 1 MAX53_AC/E MAX53_BC/E Guaranteed monotonic MAX53_ _C/E 0 3 1 12 0.5 1 1 8 Bits LSB LSB LSB ppm/C LSB ppm/C LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs
ELECTRICAL CHARACTERISTICS--Single +5V Supply (continued)
(VDD = +5V 10%, VSS = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), CREFOUT = 33F (MAX531), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS TA = +25C Reference Output Voltage VDD = 5.0V MAX531BC MAX531BE Temperature Coefficient Resistance Power-Supply Rejection Ratio Noise Voltage Minimum Required External Capacitor Input High Input Low Input Current Input Capacitance DIGITAL OUTPUT (DOUT) Output High Output Low DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Signal-to-Noise plus Distortion POWER SUPPLY Positive Supply Voltage Power-Supply Current SWITCHING CHARACTERISTICS CS Setup Time SCLK Fall to CS Fall Hold Time SCLK Fall to CS Rise Hold Time SCLK High Width SCLK Low Width DIN Setup Time DIN Hold Time DOUT Valid Propagation Delay CS High Pulse Width CLR Pulse Width CS Rise to SCLK Rise Setup Time tCSS tCSH0 tCSH1 tCH tCL tDS tDH tDO tCSW tCLR tCS1 CL = 50pF 20 25 50 20 15 0 35 35 45 0 80 ns ns ns ns ns ns ns ns ns ns ns 3 VDD IDD All inputs = 0V or VDD, MAX531 output = no load MAX538, MAX539 4.5 260 140 5.5 400 300 V A SR TA = +25C To 1/2LSB, VOUT = 2V CS = VDD, DIN = 100kHz REFIN = 1kHz, 2Vp-p (G = +1 or +2), code = FFF hex 0.15 0.25 25 5 68 V/s s nV-s dB VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 1 0.4 V V TCREFOUT RREFOUT PSRR en CMIN MAX531AC/AE/AM/BM MAX531BC/BE (Note 5) 4.5V VDD 5.5V 0.1Hz to 10kHz 3.3 400 MIN 2.024 2.017 2.013 30 30 0.5 2 300 TYP 2.048 MAX 2.072 2.079 2.083 50 ppm/C V/V Vp-p F V UNITS
MAX531/MAX538/MAX539
REFERENCE OUTPUT (REFOUT--MAX531 only)
DIGITAL INPUTS (DIN, SCLK, CS, CLR) VIH VIL IIN CIN VIN = 0V or VDD 8 2.4 0.8 1 V V A pF
SINAD
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
ELECTRICAL CHARACTERISTICS--Dual Supplies (MAX531 Only)
(VDD = +5V 10%, VSS = -5V 10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Resolution Relative Accuracy Differential Nonlinearity Bipolar Offset Error Bipolar Offset Tempco Gain Error (Unipolar or Bipolar) Gain-Error Tempco Power-Supply Rejection Ratio (Note 3) REFERENCE INPUT (REFIN) Voltage Range Input Resistance Input Capacitance AC Feedthrough Code dependent, minimum at code 555 hex Code dependent (Note 4) REFIN = 1kHz, 2.0Vp-p TA = +25C Reference Output Voltage VDD = 5.0V MAX531AC/AE/AM/BM MAX531BC/BE (Note 5) 4.5V VDD 5.5V 0.1Hz to 10kHz 3.3 400 MAX531BC MAX531BE Temperature Coefficient Resistance Power-Supply Rejection Ratio Noise Voltage Minimum Required External Capacitor DIGITAL INPUTS (DIN, SCLK, CS) Input High Input Low Input Current Input Capacitance DIGITAL OUTPUT (DOUT) Output High Output Low VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 1 0.4 V V VIH VIL IIN CIN VIN = 0V or VDD 8 2.4 0.8 1 V V A pF TCREFOUT RREFOUT PSRR en CMIN 2.024 2.017 2.013 30 30 0.5 2 300 VSS + 2 40 10 -80 2.048 2.072 2.079 2.083 50 ppm/C V/V Vp-p F V 50 VDD - 2 V k pF dB PSRR 4.5V VDD 5.5V, -5.5V VSS -4.5V SYMBOL N INL DNL VOS TCVOS GEU Tested at VDD = 5V, VSS = -5V Guaranteed monotonic BIPOFF = REFIN, MAX531_C/E BIPOFF = REFIN MAX531_C/E 1 0.4 1 3 1 MAX531AC/E MAX531BC/E CONDITIONS MIN 12 0.5 1 1 8 TYP MAX UNITS Bits LSB LSB LSB ppm/C LSB ppm/C LSB/V
REFERENCE OUTPUT (REFOUT--MAX531 only)
4
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs
ELECTRICAL CHARACTERISTICS--Dual Supplies (MAX531 Only) (continued)
(VDD = +5V 10%, VSS = -5V 10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33F, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER VOLTAGE OUTPUT (VOUT) Output Voltage Range Output Load Regulation Short-Circuit Current DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Signal-to-Noise plus Distortion POWER SUPPLY Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current SWITCHING CHARACTERISTICS CS Setup Time SCLK Fall to CS Fall Hold Time SCLK Fall to CS Rise Hold Time SCLK High Width SCLK Low Width DIN Setup Time DIN Hold Time DOUT Valid Propagation Delay CS High Pulse Width CLR Pulse Width CS Rise to SCLK Rise Setup Time Note 2: Note 3: Note 4: Note 5: tCSS tCSH0 tCSH1 tCH tCL tDS tDH tDO tCSW tCLR tCS1 CL = 50pF 20 25 50 20 15 0 35 35 45 0 80 ns ns ns ns ns ns ns ns ns ns ns VDD VSS IDD ISS All inputs = 0V or VDD, no load All inputs = 0V or VDD, no load 4.5 -5.5 260 -120 5.5 0 400 -200 V V A A SINAD SR To 1/2LSB, VOUT = 2V Step 000 hex to FFF hex REFIN = 1kHz, 2Vp-p, (G = +1) REFIN = 1kHz, 2Vp-p, (G = +2) 0.15 0.25 25 5 68 68 V/s s nV-s dB ISC MAX531 (G = +1) MAX531 (G = +2) VOUT = 2V, RL = 2k 12 VSS + 2 VSS + 0.4 VDD - 2 VDD - 0.4 1 V LSB mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX531/MAX538/MAX539
In single-supply operation, INL and GE calculated from code 11 to code 4095. Tested at VDD = +5V. This specification applies to both gain-error power-supply rejection ratio and offset-error power-supply rejection ratio. Guaranteed by design. Tested at IOUT = 100A. The reference can typically source up to 5mA (see Typical Operating Characteristics).
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
__________________________________________Typical Operating Characteristics
(VDD = +5V, VREFIN = 2.048V, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (FIRST 12 CODES)
DUAL SUPPLIES
MAX531-1
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (ALL CODES)
0.25 INTEGRAL NONLINEARITY (LSB) OUTPUT SINK CAPABILITY (mA) 16 14 12 10 8 6 4 2 0 0 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE (DECIMAL) 0
OUTPUT SINK CAPABILITY vs. OUTPUT PULL-DOWN VOLTAGE
MAX531-3
0.25 INTEGRAL NONLINEARITY (LSB) 0 -0.25 -0.50 SINGLE SUPPLY -0.75 -1.00 -1.25 0 2 4 6 8 10
0
-0.25 12 DIGITAL INPUT CODE (DECIMAL)
0.2
0.4
0.6
0.8
1.0
OUTPUT PULL-DOWN VOLTAGE (V)
OUTPUT SOURCE CAPABILITY vs. OUTPUT PULL-UP VOLTAGE
MAX531-4
ANALOG FEEDTHROUGH vs. FREQUENCY
-100 ANALOG FEEDTHROUGH (dB) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 2.045 1 10 100 1k 10k 100k 1M CODE = 000 hex
MAX531-5
OUTPUT SOURCE CAPABILITY (mA)
1 2 3 4 5 6 7 8 VDD-5 VDD-4 VDD-3 VDD-2 VDD-1
REFERENCE VOLTAGE (V)
2.050
VDD-0
-60 -40 -20
0
20
40
60
80 100
OUTPUT PULL-UP VOLTAGE (V)
FREQUENCY (Hz)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
MAX531-7
MAX531 GAIN vs. FREQUENCY
MAX531-8
MAX531 AMPLIFIER SIGNAL-TO-NOISE RATIO
REFIN = 4Vp-p SIGNAL-TO-NOISE RATIO (dB) 70 60 50 40 30 20 10 0
MAX531-9
300 280 SUPPLY CURRENT (A) 260 240 220 200 180 160 140 120 -60 -40 -20 0 20 40 60 MAX538/MAX539 MAX531
4 2 0 -2 GAIN (dB) -4 -6 -8 -10 -12 -14 REFIN = 4Vp-p
80
80 100
1
100
1k FREQUENCY (Hz)
10k
100k
10
100
1k FREQUENCY (Hz)
10k
100k
TEMPERATURE (C)
6
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MAX531-6
0
-110
MAX531 REFERENCE VOLTAGE vs. TEMPERATURE
2.055
+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs
____________________________Typical Operating Characteristics (continued)
(VDD = +5V, VREFIN = 2.048V, TA = +25C, unless otherwise noted.)
MAX531 GAIN AND PHASE vs. FREQUENCY
MAX531-10
MAX531/MAX538/MAX539
MAX531 REFERENCE OUTPUT VOLTAGE vs. REFERENCE LOAD CURRENT
MAX531-14
20
RFB CONNECTED TO AGND (G=2) RFB CONNECTED TO VOUT (G=1) GAIN
180
2.0520 2.0515 REFERENCE OUTPUT (V)
10
PHASE (degrees)
2.0510 2.0505 2.0500 2.0495
GAIN (dB)
0 PHASE -10 0
-20
-30 1 10 100 800 FREQUENCY (kHz)
-180
2.0490 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE LOAD CURRENT (mA)
DIGITAL FEEDTHROUGH
A
B
2s/div CS = HIGH A: DIN = 4Vp-p, 100kHz B: VOUT, 10mV/div
NEGATIVE SETTLING TIME (MAX531)
POSITIVE SETTLING TIME (MAX531)
A A
B
B 5s/div VDD = 5V, VREFIN = 2V, BIPOLAR CONFIGURATION A: CS RISING EDGE, 5V/div B: VOUT, NO LOAD, 1V/div 5s/div VDD = 5V, VREFIN = 2V, BIPOLAR CONFIGURATION A: CS RISING EDGE, 5V/div B: VOUT, NO LOAD, 1V/div
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+5V, Low-Power, Voltage-Output Serial 12-Bit DACs MAX531/MAX538/MAX539
____________________Pin Description
PIN MAX531 MAX538 MAX539 -- 1 -- 2 3 4 -- 5 6 -- -- 7 8 -- NAME FUNCTION
_______________Detailed Description
General DAC Discussion
The MAX531/MAX538/MAX539 use an "inverted" R-2R ladder network with a single-supply CMOS op amp to convert 12-bit digital data to analog voltage levels (see Functional Diagram). The term "inverted" describes the ladder network because the REFIN pin in current-output DACs is the summing junction, or virtual ground, of an op amp. However, such use would result in the output voltage being the inverse of the reference voltage. The MAX531/MAX538/MAX539's topology makes the output the same polarity as the reference input. An internal reset circuit forces the DAC register to reset to 000 hex on power-up. Additionally, a clear CLR pin, when held low, sets the DAC register to 000 hex. CLR operates asynchronously and independently from the chip-select (CS) pin.
1
2 3 4 5 6 7 8 9 10 11 12 13 14
BIPOFF DIN CLR SCLK CS DOUT DGND AGND REFIN REFOUT VSS VOUT VDD RFB
Bipolar Offset/Gain Resistor Serial Data Input Clear. Asynchronously sets DAC register to 000 hex. Serial Clock Input Chip Select, active low Serial Data Output for daisy-chaining Digital Ground Analog Ground Reference Input Reference Output, 2.048V Negative Power Supply DAC Output Positive Power Supply Feedback Resistor
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output, BiCMOS op amp. Input offset voltage and CMRR are trimmed to achieve better than 12-bit performance. Settling time is 25s to 0.01% of final value. The settling time is considerably longer when the DAC code is initially set to 000 hex, because at this code the op amp is completely debiased. Start from code 001 hex if necessary. The output is short-circuit protected and can drive a 2k load with more than 100pF load capacitance.
CS tCSH0 tCSS SCLK tDH tDS DIN tDO DOUT tCS1 tCH tCL tCSH1 tCSW
Figure 1. Timing Diagram
8
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs
REFOUT CREFOUT
TEK 7A22
RS CS TOTAL REFERENCE NOISE
SINGLE-POLE ROLLOFF REFERENCE NOISE (VRMS) 250 CREFOUT = 3.3F 200 150 100 50 0 0.1 1 10 FREQUENCY (kHz) 100 CREFOUT = 47F
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
MAX531-FIG02
300
1.8
REFERENCE NOISE (mVp-p)
nite at code 000 hex. REFIN's input capacitance is also code dependent and has a 50pF maximum value at several codes. Because of the code-dependent nature of reference input impedances, a high-quality, low-output-impedance amplifier (such as the MAX480 low-power, precision op amp) should be used. If an upgrade to the internal reference is required, the 2.5V MAX873A is suitable: 15mV initial accuracy, TCVOUT = 7ppm/C (max).
MAX531/MAX538/MAX539
Logic Interface
The MAX531/MAX538/MAX539 logic inputs are designed to be compatible with TTL or CMOS logic levels. However, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately 2.
Serial Clock and Update Rate
Figure 1 shows the MAX531/MAX538/MAX539 timing. The maximum serial clock rate is given by 1 / (tCH + tCL), approximately 14MHz. The digital update rate is limited by the chip-select period, which is 16 x (tCH + tCL) + tCSW. This equals a 1.14s, or 877kHz, update rate. However, the DAC settling time to 12 bits is 25s, which may limit the update rate to 40kHz for full-scale step transitions.
0 1000
Figure 2. Reference Noise vs. Frequency
Internal Reference (MAX531 only)
The on-chip reference is lesser trimmed to generate 2.048V at REFOUT. The output stage can source and sink current, so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is 5mA and sink current is 100A. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladder draws 50A maximum load current. If any other connection is made to REFOUT, ensure that the total load current is less than 100A to avoid gain errors. For applications requiring very low-noise performance, connect a 33F capacitor from REFOUT to AGND. If noise is not a concern, a lower value capacitor (3.3F min) may be used. To reduce noise further, insert a buffered RC filter between REFOUT and REFIN (Figure 2). The reference bypass capacitor, CREFOUT, is still required for reference stability. In applications not requiring the reference, connect REFOUT to VDD or use the MAX538 or MAX539 (no internal reference).
____________Applications Information
Refer to Figures 3a and 3b for typical operating connections.
Serial Interface
The MAX531/MAX538/MAX539 use a three-wire serial interface that is compatible with SPITM, QSPITM (CPOL = CPHA = 0), and MicrowireTM standards as shown in Figures 4 and 5. The DAC is programmed by writing two 8-bit words (see Figure 1 and the Functional Diagram). Sixteen bits of serial data are clocked into the DAC MSB first with the MSB preceded by four fill (dummy) bits. The four dummy bits are not normally needed. They are required only when DACs are daisy-chained. Data is clocked in on SCLK's rising edge while CS is low. The serial input data is held in a 16-bit serial shift register. On CS's rising edge, the 12 least significant bits are transferred to the DAC register and update the DAC. With CS high, data cannot be clocked into the MAX531/MAX538/MAX539. The MAX531/MAX538/MAX539 input data in 16-bit blocks. The SPI and Microwire interfaces output data in 8-bit blocks, thereby requiring two write cycles to input data to the DAC. The QSPI interface allows variable data input from eight to 16 bits, and can be loaded into the DAC in one write cycle.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
9
External Reference
An external reference in the range (VSS + 2V) to (VDD - 2V) may be used with the MAX531 in dual-supply operation. With the MAX538/MAX539 or the MAX531 in single-supply use, the reference must be positive and may not exceed VDD - 2V. The reference voltage determines the DAC's fullscale output. The DAC input resistance is code dependent and is minimum (40k) at code 555 hex and virtually infi-
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
DIN REFIN
DOUT SCLK
CS
CLR VOUT
DIN REFIN
SCLK
CS
DOUT
INVERTED R-2R DAC REFOUT 2.048V 2R 2R RFB
INVERTED R-2R DAC 2R
VOUT
MAX531
VDD VSS 0.1F 0.1F +5V
AGND DGND 33F
BIPOFF CONNECT BIPOFF TO VOUT FOR G = 1, TO AGND FOR G = 2, OR TO REFIN FOR BIPOLAR GAIN
MAX538 MAX539
AGND VDD
2R MAX539 ONLY
0V TO -5V 0.1F
+5V
Figure 3a. MAX531 Typical Operating Circuit
Figure 3b. MAX538/MAX539 Typical Operating Circuit
Daisy-Chaining Devices
The serial output, DOUT, allows cascading of two or more DACs. The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. For low power, DOUT is a CMOS output that does not require an external pull-up resistor. DOUT does not go into a high-impedance state when CS is high. DOUT changes on SCLK's falling edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of MAX531/MAX538/MAX539 DACs can be daisy-chained by connecting the DOUT of one device to the DIN of the next device in the chain. For proper timing, ensure that tCL (CS low to SCLK high) is greater than tDO + tDS.
supplies in this mode. In this range, 1LSB = (2)(VREFIN) (2-12) = (VREFIN)(2-11). The MAX539 is internally configured for unipolar gain = +2 operation.
Bipolar Configuration
A bipolar range is set up by connecting BIPOFF to REFIN and RFB to VOUT, and operating from dual (5V) supplies (Figure 8). Table 3 shows the DAC-latch contents (input) vs. VOUT (output). In this range, 1LSB = VREFIN (2-11).
Four-Quadrant Multiplication
The MAX531 can be used as a four-quadrant multiplier by connecting BIPOFF to REFIN and RFB to VOUT, using (1) an offset binary digital code, (2) bipolar power supplies, using dual power supplies, and (3) a bipolar analog input at REFIN within the range VSS + 2V to VDD - 2V, as shown in Figure 9. In general, a 12-bit DAC's output is (D) (VREFIN) (G), where "G" is the gain (+1 or +2) and "D" is the binary representation of the digital input divided by 2 12 or 4096. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost, as there are the same number of steps. The output voltage, however, has been shifted from a range of, for example, 0V to 4.096V (G = +2) to a range of -2.048V to +2.048V. Keep in mind that when using the DAC as a four-quadrant multiplier, the scale is skewed. Negative full scale is -VREFIN, while positive full scale is +VREFIN - 1LSB.
Unipolar Configuration
The MAX531 is configured for a gain of +1 (0V to VREFIN unipolar output) by connecting BIPOFF and RFB to VOUT (Figure 6). The converter operates from either single or dual supplies in this configuration. See Table 1 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = V REFIN (2 -12 ). The MAX538 is internally configured for unipolar gain = +1 operation. A gain of +2 (0V to 2VREFIN unipolar output) is set up by connecting BIPOFF to AGND and RFB to VOUT (Figure 7). Table 2 shows the DAC-latch contents vs. VOUT. The MAX531 operates from either single or dual
10
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
SCLK SK SO I/O SI SCLK SCK MOSI I/O MISO CPOL = 0, CPHA = 0 THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER . THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
MAX531 MAX538 MAX539
DIN CS DOUT
MICROWIRE PORT
MAX531 MAX538 MAX539
DIN CS DOUT
SPI PORT
Figure 4. Microwire Connection
+5V VDD BIPOFF
Figure 5. SPI/QSPI Connection
+5V VDD
REFIN REFOUT 33F AGND DGND
REFIN REFOUT 33F
MAX531
RFB
BIPOFF AGND
MAX531
RFB VOUT
VOUT
VOUT
DGND
VOUT
VSS 0V TO -5V
G = +1
VSS 0V TO -5V
G = +2
Figure 6. Unipolar Configuration (0V to +2.048V Output)
Figure 7. Unipolar Configuration (0V to +4.096V Output)
Table 1. Unipolar Binary Code Table (0V to VREFIN Output), Gain = +1
INPUT 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000 OUTPUT (VREFIN) (VREFIN) (VREFIN) 4095 4096 2049 4096
Table 2. Unipolar Binary Code Table (0V to 2VREFIN Output), Gain = +2
INPUT 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000 OUTPUT +2 (VREFIN) +2 (VREFIN) +2 (VREFIN) +2 (VREFIN) +2 (VREFIN) 4095 4096 2049 4096 2048 = +VREFIN 4096 2047 4096 1 4096
2048 = +VREFIN / 2 4096 2047 4096 1 4096
(VREFIN) (VREFIN)
OV
OV 11
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
+5V
Table 3. Bipolar (Offset Binary) Code Table (-VREFIN to +VREFIN Output)
INPUT
BIPOFF
REFIN REFOUT 33F
OUTPUT 1111 0001 0000 1111 0001 0000 (+VREFIN) (+VREFIN) 2047 2048 1 2048
1111
1111 0000 0000 1111 0000 0000
MAX531
RFB AGND DGND VOUT VOUT
1000 1000 0111 0000
0V (-VREFIN) (-VREFIN) (-VREFIN) 1 2048 2047 2048 2048 = -VREFIN 2048
-5V
Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)
0000
Single-Supply Linearity
As with any amplifier, the MAX531/MAX538/MAX539's output buffer can be positive or negative. When the offset is positive, it is easily accounted for (Figure 10). However, when the offset is negative, the buffer output cannot follow linearly when there is no negative supply. In that case, the amplifier output (VOUT) remains at ground until the DAC voltage is sufficient to overcome the offset and the output becomes positive. Normally, linearity is measured after accounting for zero error and gain error. Since, in single-supply operation, the actual value of a negative offset is unknown, it cannot be accounted for during test. Additionally, the output buffer amplifier exhibits a nonlinearity near-zero output when operating with a single supply. To account for this nonlinearity in the MAX531/MAX538/MAX539, linearity and gain error are measured from code 11 to code 4095. The output buffer's offset and nonlinear behavior do not affect monotonicity, and these DACs are guaranteed monotonic starting with code zero. In dual-supply operation, linearity and gain error are measured from code 0 to 4095.
DGND and AGND should be connected together at the chip. For the MAX531 in single-supply applications, connect VSS to AGND at the chip. The best ground connection may be achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass V DD (and V SS in dual-supply mode) with a 0.1F ceramic capacitor, connected between VDD and AGND (and between VSS and AGND). Mount with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Figures 11a and 11b illustrate the grounding and bypassing scheme described.
Saving Power
When the DAC is not being used by the system, minimize power consumption by setting the appropriate code to minimize load current. For example, in bipolar mode, with a resistive load to ground, set the DAC code to mid-scale (Table 3). If there is no output load, minimize internal loading on the reference by setting the DAC to all 0s (on the MAX531, use CLR). Under this condition, REFIN is high impedance and the op amp operates at its minimum quiescent current. Due to these low current levels, the output settling time for an input code close to 0 typically increases to 60s (no more than 100s).
Power-Supply Bypassing and Ground Management
Best system performance is obtained with printed circuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommended. The two ground planes should be connected together at the low-impedance power-supply source.
12
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
CS CLR DIN DOUT
REFOUT VDD
VSS POSITIVE OFFSET OUTPUT (LSB)
2.048V SIGNAL IN REFIN INVERTED R-2R DAC 2R VOUT
4 3 2 1 0 1 23 4 5 6 7 8 NEGATIVE OFFSET
RFB BIPOFF
MAX531
2R
DAC CODE (LSB)
Figure 9. MAX531 Connected as Four-Quadrant Multiplier. The unused REFOUT is connected to VDD.
Figure 10. Single-Supply Offset
AC Considerations
Digital Feedthrough High-speed serial data at any of the digital input or output pins may couple through the DAC package and cause internal stray capacitance to appear at the DAC output as noise, even though CS is held high (see Typical Operating Characteristics). This digital feedthrough is tested by holding CS high, transmitting 555 hex from DIN to DOUT. Analog Feedthrough Because of internal stray capacitance, higher frequency analog input signals may couple to the output as shown in the Analog Feedthrough vs. Frequency graph in the Typical Operating Characteristics. It is tested by holding CS high, setting the DAC code to all 0s, and sweeping REFIN.
ANALOG GROUND PLANE 0.1F 1 2 3 4 5 6 7 14 13 12 11 10 9 8 (a) MAX531 BYPASSING 0.1F
1 2 3 4
8 7 6 5 0.1F
(b) MAX538/MAX539 BYPASSING
Figure 11. Power-Supply Bypassing
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13
+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
__Ordering Information (continued)
PART MAX531AEPD MAX531BEPD MAX531AESD MAX531BESD MAX538ACPA MAX538BCPA MAX538ACSA MAX538BCSA MAX538BC/D MAX538AEPA MAX538BEPA MAX538AESA MAX538BESA MAX539ACPA MAX539BCPA MAX539ACSA MAX539BCSA MAX539BC/D MAX539AEPA MAX539BEPA MAX539AESA MAX539BESA TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 14 Plastic DIP 14 Plastic DIP 14 SO 14 SO 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO Dice* 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO Dice* 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO ERROR (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1 1/2 1 1/2 1 1/2 1 1/2 1 1 1/2 1 1/2 1
____Pin Configurations (continued)
TOP VIEW
BIPOFF DIN
1 2
14 RFB 13 VDD
CLR 3 SCLK 4 CS DOUT 5 6
MAX531
12 VOUT 11 VSS 10 REFOUT 9 8 REFIN AGND
DGND 7
DIP/SO
___________________Chip Topography
DIN (BIPOFF) (RFB) VDD
(CLR)
VOUT 0.120" (3.048mm) (VSS)
*Dice are specified at TA = +25C only.
SCLK CS
(REFOUT) DOUT (DGND) AGND 0.080" (2.032mm) REFIN
( ) ARE FOR MAX531 ONLY.
TRANSISTOR COUNT: 922 SUBSTRATE CONNECTED TO VDD
14
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+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs
________________________________________________________Package Information
PDIPN.EPS
MAX531/MAX538/MAX539
______________________________________________________________________________________
15
+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs MAX531/MAX538/MAX539
__________________________________________Package Information (continued)
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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